Recently, a spin transistor such as Spin-FET (field effect transistor) has been spotlighted under active investigation as a new concept transistor. A conventional semiconductor-based transistor (for example, MOSFET) controls charges in the semiconductor by use of an electric field, whereas the spin transistor simultaneously controls both charges and spins by use of spin-polarized charges. Today's investigations try to apply the spin transistor to switching devices or logic circuits through control of the spin-polarized charges. Capability of the spin transistor depends on efficiency of injecting spin-polarized electrons from a ferromagnet to a semiconductor without noise. Various investigations have been undertaken in relation to semiconductor materials or metallic materials to improve a spin injection technique.
Currently, MOSFET, one of the most important elements of a semiconductor device, is confronted with problems including difficulty in additional reduction of power and area, and a physical limit of an oxide film thereof. As one of approaches to overcome these problems, devices capable of controlling precession of the spins with voltage have been variously investigated since they were suggested in 1990's. Among these devices, the spin transistor comprises a source, a drain, and a channel to connect the source and the drain. The channel of the spin transistor can be a quantum well layer of high electron mobility, particularly a two-dimensional electron gas (2-DEG) layer. Such a spin transistor is a Datta-Das Spin FET (see “Applied Physics Letter,” Vol. 56, p. 665, 1990), and a spin transistor disclosed in U.S. Pat. No. 5,654,566 entitled “Magnetic spin injection field effect transistor and method of operation.” Meanwhile, an investigation related to spin injection from the ferromagnet into two-dimensional electron gas layer required to realize the spin transistor is reported by Hammer, et al. (see “Physical Review Letters,” Vol. 88, p. 066806, 2002). According to this investigation, the spin transistor has problems of substantial noise and very low injection efficiency. The high noise and very low injection efficiency is mainly caused by mismatch of conductivity between the metallic ferromagnet and the semiconductor, and by noise from a non-uniform junction therebetween.
FIGS. 1(a) and 1(b) are a top view and a cross-sectional view of a conventional spin transistor. Referring to FIGS. 1(a) and 1(b), a spin transistor 50 comprises a substrate part 10, a ferromagnetic source and drain 13 and 14 on the substrate part 10, and a gate 17. The gate 17 is insulated from the source 13, drain 14 and substrate part 10 by a gate oxide. The substrate part 10 is formed of a semiconductor material, and comprises a channel layer 7 which constitutes a two-dimensional electron gas layer. Spins of electrons injected from the source 13 into the channel layer 7 are controlled via a gate voltage. The electron spins reaching the drain 14 have a direction parallel or anti-parallel to a magnetization direction of the drain 14 so that resistance of the spin transistor is controlled.
FIG. 2 is across-sectional view taken along line AB of FIG. 1. Referring to FIG. 2, the substrate part 10 comprises a buffer layer 2, a carrier supply layer 4, a lower cladding layer 5, the channel layer 7, an upper cladding layer 5′, and a capping layer 6 sequentially stacked on a semi-insulating InP substrate 1. The channel layer 7 is constituted by an InAs quantum well layer. The lower cladding layer 5 comprises InGaAs and InAlAs layers 5a and 5b, and the upper cladding layer 5′ comprises InAlAs and InGaAs layers 5b′ and 5a′. Thus, both of the upper and lower cladding layers 5′ and 5 have a double cladding structure which has different energy band gaps. FIG. 2 shows an example of materials used for the respective layers.
FIG. 3 shows an energy-band structure at a junction between the source or drain 13 or 14 and the substrate part 10 in the spin transistor of FIG. 1. Referring to FIG. 3, the InGaAs 5a or 5a′ and the InAlAs 5b or 5b′ serve as energy barriers to constrain electrons within the InAs channel layer 7. In order to allow the spin electrons to be injected from the ferromagnetic source 13 into the channel layer 7, it is necessary for the spin electrons to surmount the energy barriers, that is, 5a′ and 5b′. If the channel layer is in direct contact with the ferromagnet (source) without the energy barriers, injected polarization is lowered due to influence of minor spins and back-scattering. For this reason, the energy barrier is introduced between the layers. In addition, it is necessary to form a cladding barrier surrounding the channel for easy achievement of the Rashba effect through gate control.
However, the energy barriers 5a′ and 5b′ of the double cladding structure cause an increase in contact resistance. Accordingly, the transistor suffers from deterioration in signal sensitivity, increase in power consumption, and reduction in signal-to-noise ratio. As a result, it is difficult to stably obtain clear signals from the spin transistor 50.